A Case Study of Semiconductor Export Control

 

By Erik Chmelar, PhD, PE

1. U.S. Export Control

In recent years, the semiconductor industry has been at the forefront of rising geopolitical tensions between the U.S. and China. As the U.S. broadens restrictions on exports of certain semiconductors and semiconductor manufacturing equipment (SME) to China, it is increasingly important that semiconductor companies doing business in China stay informed of changing export control laws and be able to quickly implement effective compliance measures.

While compliance with export control laws is critical to avoid significant legal and financial penalties, loss of privileges, and reputational harm, a more proactive strategy may be needed when reactive compliance alone can lead to catastrophic losses in revenue. This article reviews a proactive strategy we used to enable our client to resume development and production of advanced dynamic random-access memory (DRAM) integrated circuits (ICs) that had been entirely halted by recent U.S. export controls. The strategy also helped to alleviate billion-dollar losses in the broader U.S. SME segment that resulted from the most expansive export control action in decades.¹ This case study does not include follow-up and on-going work in this area.

 

2. October 7, 2022 IFR

The U.S. Bureau of Industry and Security (BIS) issued an interim final rule (IFR) on October 7, 2022 (hereafter “2022 IFR”) that essentially prohibited the export of items used in the development or production of ICs at facilities in China that fabricate certain logic ICs, NOT AND (NAND) memory ICs, or DRAM ICs. Specifically, the 2022 IFR prohibited certain exports relating to any of the following criteria²:

(A) Logic ICs using a nonplanar transistor architecture or with a production technology node of 16/14 nanometers or less;
(B) NAND memory ICs with 128 layers or more; or
(C) DRAM ICs using a production technology node of 18 nanometer half-pitch or less.

Put simply, the 2022 IFR prevented U.S. companies from exporting SME to China that would be used in any facility where advanced logic, NAND memory, and DRAM ICs would be developed or produced, regardless of whether the equipment would actually be used to develop or produce those advanced ICs. FIG. 1 below shows examples of (a) nonplanar transistor architectures, (b) multilayer NAND memory architectures, and (c) DRAM cell architectures.

(A) Planar and nonplanar transistor architectures for logic ICs3

(B) Multi-layer NAND architectures for NAND memory ICs4

(C) Memory-cell architectures for DRAM ICs5 FIG. 1: Examples of circuit architectures of different types of ICs

 

3. U.S. SME Segment

Revenues for the U.S. semiconductor industry in 2021 were $256 billion,⁶ with $43 billion attributed to the SME segment^{7, 8}. Three of the world’s largest SME companies are headquartered in the U.S. and account for 42% of the global SME market⁹— Applied Materials, Lam Research, and KLA Corp. These companies typically earn approximately 90% of their revenue from sales outside the United States, e.g., from exported items,¹⁰ with about 30% attributed to China¹¹.

• Applied Materials (NASDAQ: AMAT) specializes in equipment, services, and software for production of ICs, flat-panel displays, and advanced materials, with a focus on deposition, etching, and inspection technologies. Total revenues in 2021 were $24 billion,¹² with an average of 32%¹³ of revenues from China preceding the 2022 IFR.

• Lam Research (NASDAQ: LRCX) is a prominent global provider of wafer fabrication equipment and services used in the semiconductor industry, specializing in etch, deposition, and clean technologies critical to advanced semiconductor manufacturing. Total revenues in 2021 were $17 billion,¹⁴ with an average of 32%¹⁵ of revenues from China preceding the 2022 IFR.

• KLA Corp. (NASDAQ: KLAC) is a leading provider of process control and yield management solutions for the semiconductor and related industries, offering advanced inspection, metrology, and analytical systems used in semiconductor manufacturing. Total revenues in 2021 were $8 billion,¹⁶ with an average of 28%¹⁷of revenues were from China preceding the 2022 IFR.

FIG. 2 below shows a breakdown of revenues of the three major U.S. SME companies just prior to the 2022 IFR.

 

 

FIG. 2: Comparison of revenues from China and Rest of World for U.S. SME companies

 

4. Collateral Damage

The 2022 IFR intended to protect U.S. national security interests by hindering China’s military modernization and surveillance efforts, and it sought to prevent China from undercutting U.S. technology leadership or unduly interfering with commercial trade.¹⁸ However, the 2022 IFR directly affected many U.S. semiconductor segments, including SME, supercomputing, military/aerospace, and materials. The $43 billion U.S. SME segment, which is nearly four times larger than any other U.S. semiconductor manufacturing industry,¹⁹ was hit hard. For comparison, marginal impacts of the 2022 IFR on the supercomputing, military/aerospace, and materials segments are indicated below.

• Supercomputing.The global market of supercomputers was just $6.5 billion in 2021 (with just 21% from the U.S.).²⁰ A specific dollar amount of exports to China is unknown but generally understood to be negligible due to existing strict national-defense export laws.
• Military/aerospace. The global market of military/aerospace was just $6.3 billion in 2021 (with an unknown but majority percentage directed for use by U.S. military)²¹. A specific dollar amount of exports to China is unknown but generally understood to be negligible due to existing strict national-defense export laws.
• Materials. The U.S. semiconductor materials segment is much smaller than the U.S. SME segment—at $15 billion²² in 2021 compared to $43 billion—and it accounts for just 20% of the global market²³.

Returning to the U.S. SME segment, the three largest U.S. SME companies each derived approximately 30% of their respective total revenues from China prior to the 2022 IFR,²⁴ but those percentages drastically declined leading up to and following the 2022 IFR. Specifically, Applied Materials’ China revenue dropped 14% (from 32%²⁵ to 18%²⁶), Lam Research’s China revenue dropped 8% (from 32%²⁷ to 24%²⁸), and KLA Corp’s China revenue dropped 5% (from 28%²⁹ to 23%³⁰). These declines amounted to a roughly a billion dollars lost from the U.S. SME segment per quarter, as indicated by the graph of quarterly China revenues shown in FIG. 3 below.³¹

 

FIG. 3: Lost revenues resulting from the 2022 IFR

 

5. Logic v. Memory ICs

While the 2022 IFR restricted exports of SME and semiconductor manufacturing materials for logic ICs and memory ICs (i.e., NAND and DRAM), the latter caused most of the revenue loss to the U.S. SME segment. Regarding logic ICs, China’s manufacturing capabilities lagged significantly behind the 16/14 nm production technology node indicated by the 2022 IFR.³² Consequently, U.S. SME companies could continue selling equipment to China for developing and/or producing logic ICs using the less advanced production technology nodes prevalent there at the time. The situation for manufacturing of NAND memory ICs and DRAM ICs can be divided into two groups: (a) international companies with manufacturing facilities in China; and (b) China-based companies.

 

6. Clarify the Text

As indicated above, indiscriminate compliance to the text of the 2022 IFR was not a viable option for China-based companies manufacturing memory ICs that wanted to remain competitive at best or merely solvent at worst. Our task was to figure out how to comply with the 2022 IFR while simultaneously enabling the client, a DRAM manufacturer, to continue developing its advanced DRAM ICs.

We scrutinized the language of the 2022 IFR for any loopholes or ambiguities that could help. An operative portion of the 2022 IFR is reproduced below. Under the revised § 744.6 of the Export Administration Regulations (EAR), no U.S. Person may, without a license from the BIS, perform the activities of:

(c)(2)(i) Shipping, transmitting, or transferring (in-country) to or within the PRC³⁶ any item not subject to the EAR that you [(the U.S. Person)] know will be used in the “development” or “production” of integrated circuits at a semiconductor fabrication “facility” located in the PRC that fabricates integrated circuits meeting any of the following criteria:
(A) Logic integrated circuits using a nonplanar transistor architecture or with a “production” technology
node of 16/14 nanometers or less;
(B) NOT AND (NAND) memory integrated circuits with 128 layers or more; or
(C) Dynamic random-access memory (DRAM) integrated circuits using a “production” technology node
of 18 nanometer half-pitch or less.³⁷

Several approaches to narrow the language of the 2022 IFR are indicated below, which we ultimately deemed unproductive.

• U.S. Persons. The 2022 IFR describes prohibitions on the export of items by “U.S. Persons.” While EAR § 772.1 provides a broad definition, the BIS clarified in its October 28, 2022 FAQ that, for purposes of this rule, a U.S. Person is essentially any person in the United States and any juridical person organized under U.S. laws, e.g., a corporation.³⁸
• Semiconductor fabrication facility. The 2022 IFR uses the term “semiconductor fabrication facility” without defining what “facility” means. The BIS clarified in its October 28, 2022 FAQ that the definition provided in EAR § 772.1 controls, where each building of a campus may be considered a separate facility.³⁹ Thus, according to the 2022 IFR, a U.S. Person cannot export to China any items that will be used in the same building (located in China) where any category A (logic), B (NAND), or C (DRAM) ICs are produced or developed, regardless of whether those items are actually used in the production or development of the category A, B, or C ICs in that building.
• Development; production. The 2022 IFR uses the terms “development” and “production” without formal definitions. The BIS did not provide clarification on these terms at the time, so it was reasonable to assume that the definitions provided in EAR § 772.1 control. In short, “development” is related to all stages prior to serial production, and “production” means all production stages (see EAR § 772.1 for lists of examples of each).

 

7. Clarify the Technology

Instead of narrowing the language of the 2022 IFR, we determined the best approach was to clarify the definition of the regulated technology. Specifically, what does “a production technology node of 18 nanometer half-pitch or less” mean, exactly? It turns out DRAM “half-pitch” can be interpreted in several ways—M1 half-pitch, active area half-pitch, and calculated half-pitch—and their values can vary significantly. A pitch is a distance between equivalent points on adjacent repeating elements (like a center-to-center distance), and a half-pitch is simply half of the pitch.

• M1 half-pitch. Half the center-to-center distance between M1 interconnects of a memory cell. M1 is the lowest metal interconnect layer and is almost always used for the bitlines of a DRAM cell. Bitlines are interconnects that carry data, as opposed to wordlines that carry control signals.
• Active area half-pitch. Half the center-to-center distance between the active areas, or bodies, of memory cells in a direction perpendicular to the long axis of the elongated active areas. The active area is where the transistor of the ubiquitous 1-transistor, 1-capacitor (1T1C) DRAM memory cell is formed.
• Calculated half-pitch. The memory cell area divided by the cell size factor, raised to the one-half power, i.e., . The cell size factor is a normalized area based on a generalized feature size, F. For example, the cell size factor is 8 for an 8F² memory cell architecture, 6 for 6F², and so on.^40,41 More about memory-cell architectures later.

FIG. 4 below depicts a typical DRAM cell showing the bitlines (vertical), the wordlines (horizontal), and the active areas (diagonal).

 

FIG 4: DRAM cell showing bitline (BL), active area (AA), and wordline (WL) pitches

 

8. Clarify the Purpose

In the semiconductor industry, a technology node refers to a specific semiconductor manufacturing generation and its design rules, and it indicates the scaling of integrated circuits from one generation to the next. Scaling can refer to almost any parameter or metric of interest, but almost always refers to storage density (e.g., bits per square millimeter) for memory ICs and circuit speed for logic ICs (e.g., clock frequency). A technology node was historically expressed in terms of microns or nanometers (e.g., 0.13 µm, 90 nm, etc.), and it correlated to some tiny, fabricated feature of an IC like M1 half-pitch for DRAM ICs or transistor gate-length for logic ICs.

As indicated above, DRAM M1 half-pitch is half the center-to-center distance between the lowest metal layer of a memory cell, i.e., M1 interconnects. In the early days of semiconductors, this definition worked well in describing the scaling between DRAM technology nodes because M1 half-pitch consistently and predictably scaled (i.e., shrank) with each subsequent generation, and it correlated well with storage density. In fact, by 1999, DRAM M1 half-pitch was declared by the International Technology Roadmap for Semiconductors (ITRS)⁴² to be the standard way to designate DRAM technology nodes.⁴³

But the usefulness of M1 half-pitch to define DRAM technology nodes was short-lived due to a disappearing correlation between M1 half-pitch and the chosen micron or nanometer number designating a technology node.⁴⁴ This is partly the reason why seemingly arbitrary alphanumeric and Greek letters are commonly used to describe today’s technology nodes (e.g., 1α, 1β, etc.).

To be clear, the key aspect of a designator for a technology node is not some tenuous connection to a fabricated feature size like DRAM M1 half-pitch, but its ability to accurately indicate the scaling between semiconductor technology nodes. This was emphasized in the 2005 ITRS, which stated:

[W]e no longer use the term “technology node.” Instead, each distinct scaling feature is specifically referenced as such. Note that, for some degree of continuity, we are still showing DRAM M1 half-pitch at the top of many tables, but it is no longer described as the measure of “technology node.” It is just one among several historical indicators of IC scaling.⁴⁵

Accordingly, the half-pitch referred to in the 2022 IFR should faithfully indicate technology-node scaling, because a half-pitch that fails to do so could lead to ambiguous application of the 2022 IFR—and potentially excessive economic damage to the U.S. SME industry.

Notwithstanding that the semiconductor industry had long since abandoned M1 half-pitch as the designator for technology nodes,⁴⁶ M1 half-pitch could be ruled out with a simple technical argument. Practically all DRAM memory cells today utilize a 6F² architecture. One (older) version of the 6F² architecture (referred to as 2×3) comprises wordlines oriented perpendicular and above elongated active areas, and bitlines oriented colinear with the active areas and above the wordlines, as shown in FIG. 5(B) below. Another (newer) version of the 6F² architecture (referred to as 3×2) comprises the same layering and same bitline (M1) pitch as the older 2×3, but the elongated active areas are staggered and slanted at an angle with respect to the bitlines, as shown in FIG. 5(C) below. This purely geometric maneuver allows the wordlines to be brought closer to each other, thereby reducing the memory cell area without reducing the bitline pitch, i.e., without reducing the M1 half-pitch. In other words, the storage density—the key scaling metric for designating DRAM technology nodes—is independent of M1 half-pitch. Thus, M1 half-pitch does not faithfully indicate technology-node scaling.

(A) 8F2 DRAM cell	(B) 2×3 6F2 DRAM cell	(C) 3×2 6F2 DRAM cell
FIG 5: DRAM cell architectures showing different cell areas

 

A similar argument could be made to rule out active area half-pitch. The 8F² “folded bitline” architecture was mainstream until approximately 2008 when it was supplanted by the 2×3 6F² “open bitline” architecture.⁴⁷ In the 8F² architecture, showin in FIG. 5(A) above, the elongated active areas are staggered along their long axes so that a given wordline contacts only odd or only even active areas in the memory array. In contrast, in the 2×3 6F² architecture, the ends of the elongated active areas are aligned so that a given wordline contacts both odd and even active areas in the memory array. However, in both architectures, the wordlines are oriented perpendicular and above elongated active areas, and bitlines are oriented colinear with the active areas and above the wordlines. Thus, for the same active area half-pitch, the 8F²architecture has a normalized area of 8 and the 6F² architecture has a normalized area of 6. This is a 25% reduction in memory cell size yielding a 33% improvement in storage density⁴⁸—the key scaling metric for designating DRAM technology nodes—that is achieved by architectural improvements independent of active area half-pitch. Thus, active area half-pitch does not faithfully indicate technology-node scaling.

The industry has been working toward a 4F² architecture for several decades, but additional semiconductor manufacturing advancements are required, such as those concerning vertical transistor structures, high-κ dielectrics, and so on.⁴⁹ There are two implications. First, parallel to the argument above, the scaling in storage density by transitioning from 6F²to 4F² is due to architectural improvements independent of the active area half-pitch. Second, the transition from 6F² to 4F² will occur at some future technology node that encompasses the required additional semiconductor manufacturing advancements that have practically nothing to do with patterning a smaller active area onto a silicon substrate. For these additional reasons, active area half-pitch does not faithfully indicate technology-node scaling.

That leaves calculated half-pitch as the best interpretation of “half-pitch” in the 2022 IFR. One argument could be made based entirely on the semiconductor industry’s consensus on redefining DRAM half-pitch from M1 half-pitch to calculated half-pitch according to the 2017 International Roadmap for Devices and Systems (IDRS):

The definition of DRAM Half pitch has been changed from this edition. Because of 6F2 DRAM cell, BL pitch is no more critical dimension. . . . Calculated half pitch is use [sic] the following equation “Calculated half pitch= (Cell Area/ Call [sic] size factor)^0.5.”⁵⁰

However, a better argument was to show that calculated half-pitch faithfully indicates technology-node scaling. To repeat, calculated half-pitch is defined as .⁵¹ Cell area accounts for process-related changes in any relevant feature sizes—such as bitline pitch, wordline pitch, and active area pitch—as well changes due to geometric maneuvering, such as staggering and slanting the active areas. Further, cell size factor accounts for changes in memory cell architecture, such as the evolution from 8F² to 6F² and eventually to 4F². In this manner, calculated half-pitch faithfully indicates storage density, which is the key scaling metric for designating DRAM technology nodes. Consequently, it is reasonable to interpret category C the 2022 IFR as DRAM ICs using “a ‘production’ technology node of 18 nanometer calculatedhalf-pitch or less.”

 

9. Draft Mutually Beneficial Opinions

While distinctions between various half-pitches may seem arbitrary or confusing, they were critically important to determining whether U.S. SME companies could legally export advanced SME to China-based manufacturers of advanced ICs. As indicated above, DRAM half-pitch historically referred to the smallest feature size in the memory cell. In the ubiquitous 3×2 6F² architecture, that is typically the active area pitch because of staggering and slanting the active areas. But, as explained above, active area half pitch does not faithfully represent memory-cell size across architectures, so that interpretation of “half-pitch” can result in inaccurate application of the 2022 IFR. Further, calculated half-pitch—which does faithfully represent memory-cell size across architectures—is typically larger than active area half-pitch for the 3×2 6F² architecture. Thus, interpreting “half-pitch” as calculated half-pitch was a win for U.S. SME companies because it enabled objective and accurate compliance with the 2022 IFR, and it was a win for the China-based DRAM manufacturers because it enabled them to manufacture advanced DRAM ICs that would otherwise not be possible.

We drafted legal opinions based on the preceding material to guide U.S. SME companies in accurately interpreting the 2022 IFR with respect to the development and production of advanced DRAM ICs. We also drafted legal opinions that included semiconductor metrology data of actual DRAM ICs produced by our client showing a calculated half-pitch greater than 18 nm. Through the first couple quarters of 2023 we continued to advance our calculated half-pitch interpretation, and we obtained additional third-party semiconductor metrology data to assure the U.S. SME companies that any SME exported to our client’s facilities would be in compliance with the 2022 IFR. At least several U.S. SME companies consulted with the BIS for further assurances, and by mid-2023, it appeared our strategy had been successful. Indeed, On October 25, 2023, the BIS issued a new IFR (hereafter “2023 IFR”) that formally adopted our interpretation of half-pitch in the 2022 IFR as calculated half-pitch, the text of which is reproduced below (emphasis added).⁵²

 

10. Conclusion

As indicated in the graph of quarterly revenues of U.S. SME companies shown in FIG. 3 above, the U.S. SME companies had begun exporting advanced SME to China-based semiconductor manufacturing companies well before issuance of the 2023 IFR. Our proactive strategy for the 2022 IFR not only helped to revive our client’s competitiveness in the global DRAM IC market, but it helped to alleviate the billion-dollar losses incurred by the U.S. SME companies.

 

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